• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The integrated circuit (IC) comprises a substrate (S) and at least one MOS transistor (TGE) comprising a gate region (RG) buried in a trench (T) of the substrate (S), opening on an upper face (FS) of the substrate (S), and surrounded by a dielectric region (RDI) lining the inner walls of the trench (T), a source region (RS) and a drain region (RD) located respectively in the substrate (S) of on either side of the trench (T) in the vicinity of said upper face (FS), said dielectric region (RDI) having an upper dielectric zone (ZDS) located at least partially between an upper portion (PS) of the region of grid (RG) and the source (RS) and drain (RD) regions, and a lower dielectric zone (ZDI) less thick than the upper dielectric zone (ZDS) and situated between a lower part (PI) of the region of grid (RG) and the substrate (S).
    公开号:FR3038774A1
    申请号:FR1556470
    申请日:2015-07-08
    公开日:2017-01-13
    发明作者:Julien Delalleau；Christian Rivero
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    Method for producing a high-voltage transistor with reduced space requirement, and corresponding integrated circuit
    Modes of implementation and embodiment of the invention relate to integrated circuits, and more particularly the manufacture of MOS transistors capable of holding a high voltage, for example of the order of 15 volts, between the drain and the gate.
    Such transistors can be used, for example, in non-volatile memories of the electrically erasable and programmable type (EEPROM).
    In general, a high voltage MOS transistor has a planar structure with an extended drain (MOS "drift") so as to have a high breakdown voltage ("breakdown voltage").
    For example, an extended-drain MOS transistor generally comprises a further "drift" drain region having a lower dopant density between the gate region and the normal drain region of the MOS transistor so as to avoid an excessively high electric field. when applying a high voltage between the gate and the drain of the MOS transistor.
    However, since the gate dielectric layer of an extended drain MOS transistor is generally uniform and thin, the end portion of this dielectric layer located in the vicinity of the drain may still be slammed due to a phenomenon of electric field crowding when applying a high voltage.
    Moreover, a planar extended drain MOS transistor is also expensive in terms of surface area.
    Thus, according to a mode of implementation and implementation, it is proposed to reduce the silicon footprint of a high-voltage MOS transistor while providing electrical performance equivalent to or greater than that of a conventional planar transistor.
    According to one aspect, there is provided an integrated circuit, comprising a substrate and at least one MOS transistor comprising a gate region buried in a trench of the substrate, opening on an upper face of the substrate, and surrounded by a dielectric region lining the internal walls. of the trench, a source region and a drain region located respectively in the substrate on either side of the trench in the vicinity of said upper face, said dielectric region having an upper dielectric zone located at least partially between an upper portion of the gate region and the source and drain regions, and a lower dielectric region less thick than the upper dielectric region and located between a lower portion of the gate region and the substrate.
    Such a buried gate MOS transistor with a non-uniform gate dielectric dimension not only makes it possible to maintain the electrical performance of the MOS transistor by using the relatively thin lower dielectric zone between the channel region and the gate region, but also reduce the risk of breakdown by using the thicker upper dielectric zone between the drain region and the gate region.
    In addition, such a high voltage transistor does not require insulating spacers. As an indication, the maximum thickness of the upper dielectric zone may be of the order of 20 nm, and is greater than the average thickness of 15 nm of a gate dielectric layer of a high voltage MOS transistor. planar structure.
    Advantageously, the vertical structure of the gate region of the buried gate MOS transistor also makes it possible to reduce the silicon footprint of the transistor, for example up to 30%, and this structure is applicable for the two types, N and P, of MOS transistors.
    According to a possible variant, the gate region comprises a gate recess zone between the lower part and the upper part of the gate region.
    According to another possible variant, the dielectric region comprises a dielectric recess zone between the lower dielectric zone and the upper dielectric zone.
    In another aspect, there is provided a method of manufacturing a MOS transistor, comprising forming a buried gate region in a trench of the substrate, opening on an upper face of the substrate, forming a source region and a drain region respectively located in the substrate on either side of the trench in the vicinity of said upper face, forming a dielectric region lining the inner walls of the trench, surrounding the gate region and having an upper dielectric zone located at least partially between an upper portion of the gate region and the source and drain regions, and a lower dielectric zone less thick than the upper dielectric zone and located between a lower portion of the gate region and the substrate.
    Such a manufacturing method completely compatible with a CMOS production stream advantageously makes it possible to reduce the number of masks used.
    According to one possible variant, the formation of the gate region comprises a formation of a gate recess zone between the lower part and the upper part of the gate region.
    According to an embodiment applicable to this variant, the formations of the dielectric region and of the gate region comprise a formation of a first dielectric layer lining the inner wall of the trench, a formation of a sacrificial gate region. covering the first dielectric layer and filling the trench, partially removing the sacrificial gate region so as to obtain the lower part of the gate region surrounded by the lower dielectric zone, forming a second dielectric layer covering the first layer dielectric and the lower part of the gate region, a withdrawal of the portion of the second dielectric layer covering the lower portion of the gate region so as to obtain the upper dielectric zone, and a formation of the gate region comprising the portion upper separated from the lower part by the drop zone grid and surrounded by the upper and lower dielectric zones.
    According to another possible variant, the formation of the dielectric region comprises a dielectric recess zone between the lower dielectric zone and the upper dielectric zone.
    According to an implementation mode applicable to this other variant, the formations of the dielectric region and the gate region may comprise a partial etching of an isolation trench leaving on its side walls a first dielectric layer and an etching partially of the underlying substrate so as to obtain said trench, a formation on the first dielectric layer and on the walls of the lower portion of the trench of a second dielectric layer so as to obtain said dielectric step region, and a filling the trench with a grate material. Other advantages and characteristics of the invention will become apparent upon studying the detailed description of embodiments, taken as non-limiting examples and illustrated by the appended drawings in which: FIGS. 1 to 16 illustrate schematic various modes of implementation and embodiment of the invention.
    FIG. 1 illustrates a substrate S, for example made of silicon and with a thickness E of the order of 2 μm, provided for an embodiment of at least one TGE buried gate MOS transistor according to the invention.
    Firstly, by oxidation, a sacrificial CS layer of the S1O2 type known to those skilled in the art under the name "SACOX", for example of the order of a few nanometers, is formed on the entire upper surface FS of the substrate S (Figure 2).
    A layer of CNS silicon nitride is then conventionally and known per se.
    This nitride layer CNS is then used as a hard mask in a subsequent step of anisotropic etching to form a trench T in the substrate S. The opening OUV of the trench T near the upper face FS of the substrate S is for example of the order of 200 nm and the depth of the trench T is for example of the order of 0.5 pm.
    Then, a first dielectric layer CD1 is formed by re-oxidation, for example of the order of a few nanometers, lining the entire inner wall of the trench T, as can be seen in FIG.
    FIG. 4 illustrates a step of depositing a RSG gate sacrificial region, for example made of polysilicon, in the trench T and on the entire substrate S. Such a deposit is conventional and known per se.
    In FIG. 5, the RSG gate sacrificial region deposited in the preceding step is partially removed by a conventional anisotropic dry etching step so as to obtain a lower part PI. This lower part PI is surrounded by a lower dielectric zone ZDI lining the inner wall of the trench T.
    A second dielectric layer CD2 covering the upper zone of the first dielectric layer CD1 and the lower part PI, as shown in FIG. 6, is then reformed by oxide growth.
    Then, a partial removal of the second dielectric layer CD2 is carried out, by anisotropic dry etching, in order to obtain an upper dielectric zone ZDS, located above the lower dielectric zone ZDI, and thicker than the lower dielectric zone ZDI (Figure 7).
    This difference in thickness between the upper dielectric zone ZDS and the lower dielectric zone ZDI offers a double advantage over the electrical performance of the future MOS transistor, as will be seen in more detail below.
    For forming an upper portion PS of the gate region RG, the lower portion P1 of the gate region RG located in the trench can be completely removed in a first step (FIG. time by a conventional gate deposition step, the complete gate region RG having the lower part PI surrounded by the lower dielectric zone ZDI and the upper part PS surrounded by the upper dielectric zone ZDS, as shown in FIG. 9.
    Alternatively, an upper part PS of the grid region RG above the lower part PI could be directly formed by a conventional grid deposition step to obtain the same grid region RG as that illustrated in FIG. 9. .
    After chemical-mechanical polishing, the gate region RS having a lower portion P1 and an upper portion PS respectively surrounded by the lower dielectric zones ZDI and upper ZDS lining the trench T. are obtained (FIG. 10).
    It should be noted that since the upper dielectric zone ZDS is thicker than the lower dielectric zone ZDI, the gate region RS has a gate recess zone ZDG between the lower part PI and the upper part PS.
    Then, by conventional steps known per se, a source region RS and a drain region RD respectively located in the substrate S on either side of the trench T in the vicinity of said upper surface FS of the substrate S are formed. .
    As a result, a buried gate MOS transistor TGE implemented in an integrated circuit IC is finally obtained, as illustrated in FIG. 11.
    It should be noted that the upper dielectric zone ZDS is located at least partially between the upper part PS of the gate region RG and the source regions RS and drain RD.
    The TGE transistor therefore comprises a buried gate with a U-shaped CNL channel.
    The fact that the upper dielectric zone ZDS is relatively thicker, for example with a maximum thickness of the order of 20 nm, makes it possible to obtain a breakdown voltage ("breakdown voltage" in English) high between the drain and the gate.
    The fact that the lower dielectric zone ZDI remains thin, for example 9 nm thick, over most of the CNL channel ensures good electrical performance of the MOS transistor TGE.
    It is possible to achieve an impression reduction of up to 30% compared to a planar MOS transistor.
    In a possible variant illustrated in FIGS. 12 to 19, a TGE buried gate MOS transistor can be formed from a conventional shallow insulation trench (STI) ("Shallow Trench Isolation").
    FIG. 12 illustrates such an isolation trench TS opening on the upper face FS of the substrate S and filled with an insulating material MI, for example silicon dioxide.
    The edges of this isolation trench TS form de facto an initial part ΡΙΝΙ of the future trench T of the MOS transistor with buried gate TGE.
    On board, anisotropic etching removes a portion of the insulating material MI and a portion of the substrate S located below the initial portion ΡΙΝΙ so as to obtain an additional portion PSUP of the trench T (FIG. 13).
    A ZDINI portion of the MI material remains on the edges of the initial portion ΡΙΝΙ of the trench T and forms a first dielectric layer.
    Then, by oxidation, a second dielectric layer CDS covering the ZDINI part and lining the supplementary part PSUP of the trench T is formed so as to obtain a lower dielectric zone ZDI lining the additional part PSUP of the trench T and an upper dielectric zone ZDS lining the initial part ΡΙΝΙ of the trench T (Figure 14).
    It will be noted that the dielectric region RDI comprises a dielectric recess zone ZDD between the lower dielectric zone ZDI and the upper dielectric zone ZDS.
    After a conventional step of deposition of the gate material, for example poly-silicon, the grid region RG surrounded by the upper dielectric zone ZDS is formed in the initial portion ΡΙΝΙ of the trench T and by the lower dielectric zone ZDI in the additional part PS of the trench T, as illustrated in Figure 15.
    FIG. 16 illustrates the buried grid MOS transistor TGE produced in the integrated circuit IC after the conventional formation of the drain regions RD and source RS.
    权利要求:
    Claims (8)
    [1" id="c-fr-0001]
    An integrated circuit (IC), comprising a substrate (S) and at least one MOS transistor (TGE) comprising a gate region (RG) buried in a trench (T) of the substrate (S), opening on an upper face ( FS) of the substrate (S), and surrounded by a dielectric region (RDI) lining the inner walls of the trench (T), a source region (RS) and a drain region (RD) located respectively in the substrate (S). ) on either side of the trench (T) in the vicinity of said upper face (FS), said dielectric region (RDI) having an upper dielectric zone (ZDS) located at least partially between an upper part (PS) of the gate region (RG) and the source (RS) and drain (RD) regions, and a lower dielectric zone (ZDI) less thick than the upper dielectric zone (ZDS) and situated between a lower part (PI) of the Grid region (RG) and the substrate (S).
    [2" id="c-fr-0002]
    An integrated circuit (IC) according to claim 1, wherein the gate region (RG) includes a gate recess zone (ZDG) between the lower portion (PI) and the upper portion (PS) of the gate region. (RG).
    [3" id="c-fr-0003]
    An integrated circuit (IC) according to claim 1, wherein the dielectric region (RDI) comprises a dielectric step region (ZDD) between the lower dielectric zone (ZDI) and the upper dielectric zone (ZDS).
    [4" id="c-fr-0004]
    4. A method of manufacturing a MOS transistor (TGE), comprising a formation of a gate region (RG) buried in a trench (T) of the substrate (S), opening on an upper face (FS) of the substrate ( S), a formation of a source region (RS) and a drain region (RD) located respectively in the substrate (S) on either side of the trench (T) in the vicinity of said upper face (FS), a formation of a dielectric region (RDI) lining the inner walls of the trench (T), surrounding the gate region (RG) and having an upper dielectric zone (ZDS) at least partially between an upper portion (PS) of the gate region (RG) and the source (RS) and drain (RD) regions, and a lower dielectric zone (ZDI) less thick than the upper dielectric zone (ZDS) and located between a lower part (PI) of the gate region (RG) and the substrate (S).
    [5" id="c-fr-0005]
    The method according to claim 4, wherein forming the gate region (RG) comprises forming a gate recess zone (ZDG) between the lower part (PI) and the upper part (PS) of the gate region. grid region (RG).
    [6" id="c-fr-0006]
    The method of claim 5, wherein the dielectric region (RDI) and grid region (RG) formations comprise a formation of a first dielectric layer (CD1) lining the inner wall of the trench (T). , forming a sacrificial gate region (RSG) covering the first dielectric layer (CD1) and filling the trench (T), partially removing the gate sacrificial region (RSG) so as to obtain the lower part (PI) ) of the gate region (RG) surrounded by the lower dielectric zone (ZDI), a formation of a second dielectric layer (CD2) covering the first dielectric layer (CD1) and the lower portion (PI) of the gate region (RG), removing the portion of the second dielectric layer (CD2) covering the lower portion (PI) of the gate region (RG) so as to obtain the upper dielectric zone (ZDS), and formation of the region Grid (R G) having the upper part (PS) separated from the lower part (P1) by the gate recess zone (ZDG) and surrounded by the upper (ZDS) and lower (ZDI) dielectric zones.
    [7" id="c-fr-0007]
    The method of claim 4 wherein the formation of the dielectric region (RDI) comprises a dielectric step region (ZDD) between the lower dielectric zone (ZDI) and the upper dielectric zone (ZDS).
    [8" id="c-fr-0008]
    8. The method of claim 7, wherein the formations of the dielectric region (RDI) and the gate region (RG) comprise a partial etching of an isolation trench (TS) leaving on these side walls a first dielectric layer (ZDINI) and partially etching the underlying substrate (S) so as to obtain said trench (T), a formation on the first dielectric layer (ZDINI) and on the walls of the lower part of the trench (T ) of a second dielectric layer (CDS) so as to obtain said dielectric step region (ZDD), and a filling of the trench with a gate material.
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    法律状态:
    2016-06-22| PLFP| Fee payment|Year of fee payment: 2 |
    2017-01-13| PLSC| Publication of the preliminary search report|Effective date: 20170113 |
    2017-06-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-06-21| PLFP| Fee payment|Year of fee payment: 4 |
    2019-06-21| PLFP| Fee payment|Year of fee payment: 5 |
    2020-06-23| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1556470|2015-07-08|
    FR1556470A|FR3038774B1|2015-07-08|2015-07-08|METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH A REDUCED SIZE, AND CORRESPONDING INTEGRATED CIRCUIT|FR1556470A| FR3038774B1|2015-07-08|2015-07-08|METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH A REDUCED SIZE, AND CORRESPONDING INTEGRATED CIRCUIT|
    CN201620136399.0U| CN205406528U|2015-07-08|2016-02-23|Integrated circuit|
    CN201610099471.1A| CN106409905A|2015-07-08|2016-02-23|Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit|
    US15/068,732| US20170012104A1|2015-07-08|2016-03-14|Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit|
    US15/454,184| US9978847B2|2015-07-08|2017-03-09|Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit|
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